DDR5 SDRAM is the next generation memory and is sure to replace DDR4. DDR5 stands for Double Data Rate 5. This post will discuss in detail about what is DDR5 SDRAM (Double Data Rate 5 SDRAM), its features, architecture, how it works, applications & advantages.
What is DDR5 SDRAM
Officially, DDR5 stands for Double Data Rate 5 and SDRAM is abbreviated for Synchronous Dynamic – Random Access Memory. Double Data Rate 5 is the fifth generation RAM that promises great speed by doubling its bandwidth. It is also being created to reduce memory module voltage which will consequently reduce power consumption.
The estimated release date is late 2020. Various companies have started working on this RAM however results are not yet meeting the speed that has been originally guaranteed. The first DDR5 chip was released by SK Hynix with 16 GB capacity.
Fig. 1 – Introduction to DDR5 SDRAM
This RAM will still keep the design with 288 pins. The voltage will, however, drop to 1.1V. This memory chip will be using a second-generation 10 nm-class fabrication technology. It will have 4 metal layers and its Die size is 76.22 mm². DDR5 SDRAM uses 2 Ranks with 8 Bank Groups consisting of 32 Banks. Number of Banks per Bank Group is 4.
Banks form a next logical unit known as Rank. Memory Rank refers to a set of DRAM Chips connected to same Chip select. DDR5’s Burst Length is increased to 16. Burst Length refers to Data Bus Width i.e. the number of bytes that can be transferred in a Burst.
Fig. 2 – Representation of Bank Group and Memory Rank in DDR5 SDRAM
The DDR5 memory will provide users with higher performance. This means that it will operate at higher frequencies. High frequencies can create clock instability. So, in order to reduce this, DLL (Delay Locked Loop) / PLL (Phase Locked Loop) circuit is used.
These circuits work by continuously comparing and adjusting the two signals i.e. clock signal and output data signal and provides feedback so that Transmission and Reception takes place at a fixed time. The DDR5 RAM when compared to its predecessor DDR4, features a revised Forward Feedback Equalization circuit. This also help in stabilizing clock problems due to high frequencies.
The DDR5 promises to reach consumers with double the capacity of DDR4. This means that it will have the capacity to hold 32 GB – 64 GB instead of the 16 GB of DDR4. This larger memory is expected to increase the battery life of our device. And naturally, an energy-saving RAM is important for all our devices that work on battery power such as headphones and mobile phones, laptops and tablets.
Features of DDR5 SDRAM
The features and comparison of DDR5 with DDR4 is as shown in the figure below:
Fig. 3 – Comparison of Features of DDR4 and DDR5
Architecture of DDR5 SDRAM
DDR5 SDRAM is mounted on DIMM (Dual In-Line Memory Module) that is installed on systems Motherboard. Hence DDR5 Architecture is alternatively called as DDR5 DIMM Architecture. It consists of several components like:
- PMIC (Power Management IC)
- Bank Group
- Data Buffers
- RCD (Register Clock Driver)
- Memory Controller
PMIC (Power Management IC)
DDR5 SDRAM will have a 12 V PMIC (Power Management IC). It is specially designed for Computers and embedding platforms. It helps in reducing system power and offers greater performance and reliability. It is independent and features four step-down switching regulators. Power management interface may be configured to enable the host to read/write data from/to a power management circuit of a Dual In-line Memory Module (DIMM). It is disabled at power on.
There are two Channels on the right and left side of the DIMM. Each Channel is 40 bits wide which includes 8 ECC bits and 32 Data bits. ECC (Error Correction Code) detects and corrects data corruption, if any. Having two separate Channels improves memory access efficiency.
Memory Rank refers to a set of DRAM Chips connected to same Chip select. It is also defined as the area of Data created using some or all of the memory chips on a module.
It is the logical unit of storage and 4 Banks form a Bank Group. DDR5 SDRAM uses 8 Bank groups.
They are used to reduce the effective load on the data-bus. Each module has a Data Buffer Chip which is connected to the Bus. All the clock, command and control signals are transferred to the Buffers through RCD. It re-drives all the signals to the multiple Ranks of DRAM. Data Buffers are configured by the Register Clock Driver via buffer communication bus.
RCD (Register Clock Driver)
Register Clock Driver uses multiple Data Buffers to buffer incoming Data Signals (DQ) and Data Strobe Signal (DQS) between the host Memory Controller and DRAM. It handles all the reads and writes to the Memory chips via buffers by sending clock, control and command signals. RCD can be configured from the host Memory Controller, either through the command/address bus or via a serial management bus.
Memory Controller in the processor transmits the signals in the form of data packets to Buffers. SDRAM devices has to be refreshed periodically to save valid data and the Memory Controller issues Refresh commands periodically. The refresh command in DDR5 is called ‘SAME-BANK REFRESH’ command. It works in conjunction with ‘ALL- BANK REFRESH’ command which was used in DDR4.
Fig. 4 – Architecture of DDR5 SDRAM
How does DDR5 SDRAM Work
When the CPU issues a read/write command to memory, the requested row is activated and copied to the row buffer of the corresponding Bank. Each physical address (PA) in the system is mapped to a specific channel/DIMM and to Data Buffers. Read and/or write commands are issued to the active row by implementing Burst modes.
The row is pre-charged and stores back into the memory array. The read/write request is issued on the command bus and the data is returned if it’s a Read Request. If it is a ‘Write’ request, then data is sent on the data bus along with ‘Write’ command.
DDR5 SDRAM implements Error Correction Code (ECC) and Error check and Scrub (ECS) functions to detect errors and writes back corrected data if an error occurs. The data bus transfers data on both rising and falling edge of the clock signal. Memory Controller issues Refresh commands periodically to not lose the data.
Fig. 5 – Representation of Working of DDR5 SDRAM
Applications of DDR5 SDRAM
Now let us see how this SDRAM could be applied to certain devices:
Generally, mobile devices and smartphones use low power memory since they require low power consumption to work. So, in this case, we can safely say that we can expect the DDR5 to operate at up to 6400 MT/s. We should soon be seeing DDR memory kits which will hit the 6400 MHz mark. With the above on mind, however, Samsung has already published news about the creation of their 10-nanometer class, 8 GB DDR5 SDRAM. This is the first of its kind and it can be installed in mobile devices. It has an 8 GB capacity and a data rate of up to 1.5 times faster than DDR4 RAM
In Gaming PC’s
News of a new DDR surely sparked great interest in the technical world. Even though DDR4 memory is still relatively new to the consumer’s market, we have DDR5 to look forward to. In fact, an increase of 85% memory performance and twice the memory density has been promised over DDR4. Developers promise twice the performance with capacities of 32 GB on every single stick.
Advantages of DDR5 SDRAM
The advantages include:
- Higher bandwidth: from 3200 – 6400 MT/sec data rate.
- 1.6 – 3.2 GHz clock rate.
- Lower voltage consumption: 1.1V.
- Power efficiency: better battery power management.
- Higher capacity DIMM’S – 32 GB/64 GB when compared to 16 GB on DDR4
- Larger Memory: burst length BC8 (Committed Burst), BL16 (Burst Length).
- Improved and refreshed granularity.
- Two independent 40-bit channels per module.
- Increased Bank Groups and Banks by two times for increased performance.
Disadvantages of DDR5 SDRAM
The advantages in migrating from DDR4 to the new and improved DDR5 are many. However, there are also disadvantages to this and they are:
- Initially not much is expected. There will not be much of a difference between the already fast and cheap DDR4 modules.
- DDR5 high-speed signals: designers will need to make sure that the motherboard and DIMM’S can take these high-speed signals.
- Higher clock and data rates: RAM designers need to ensure that the PDN (power delivery network) can take the higher speed with good signal integrity.
- Command Address Bus (CA): The RCD CA bus receivers will need DFE (Differential Feedback Equalization) options to provide good signal reception.
- The new and improved DDR5 memory will also need good built-in support on motherboards and chips.
We have drafted a short document where we tried to include all the dreams that we are being fed regarding this new DDR5 memory module. We have to wait and see what RAM developers will come out with. Even though we are quite sure that price will be higher than that of DDR4, we hope that once the initial rush calms down the price will stabilize itself also. We are sure that both developers and designers have both knowledge and expertise to create a DRAM that will stupefy us, one which will amaze us with all the speed and power that have been spoken about.